module dut(
     input        clk
    ,input        rstn
    ,input        rx_dv
    ,input  [7:0] rxd
    ,output [7:0] txd
    ,output       tx_en
);

reg [7:0] txd_reg;
reg tx_en_reg;

always @(posedge clk) begin
    if(~rstn)begin
        txd_reg   <= 8'h0;
        tx_en_reg <= 1'b0;
    end else begin 
        txd_reg   <= rxd;
        tx_en_reg <= rx_dv;
    end
end

assign txd = txd_reg;
assign tx_en = tx_en_reg;

endmodule
